Hi everyone, I was wondering why there were so few sources of VHDL around but many Verilogs and went on to search the differences between the two. However, all I get are either out of date or highly biased reviews towards Verilog. It seems that some time ago Verilog was the HDL of choice but now things may have changed since VHDL was made a standard (that's imho). Does anybody know the current situation? Thank you very much for any of your replies. Cheers, Chris

While we were developing real pure low power ASICs on SUN workstations not based on FPGA designs, verilog HDL was the choice because all ASIC fabs requested verilog based verification sources. well i guess it also depends what language you prefere or are used too. for me VHDL is too much typo so i use verilog hdl.

Havent really used Verilog other than browsing round some code, but it seems to me that its structors much more like C than VHDL, so many people probably prefer it as they see it as easier to learn. VHDL is strongly typed so you cant get away with alot. VHDL is great for typing exactly what you mean. It does mean VHDL is quite verbose though. Impressions I get online from people that do both, VHDL can do things quite neatly that verilog struggles with. I was always under the impressions that its a bit of an ASIC vs FPGA thing : verilog was better for asics and VHDL better for FPGA. Also, I think VHDL can be better at abstracting things and behavioural models (though many people talk about systemverilog being as good if not better).

Just to Add: Both Verilog and VHDL have been made into standards. VHDL in 1987, 1993, 2001 and 2008. Verilog in 1995, 1998 and 2001

I used to be a die hard VHDL user but after giving Verilog a chance I can say that I hope to never see another line of VHDL ever again :) Like others have said VHDL is a more strict language which can be a good thing for catching mistakes. Verilog is a more relaxed and compact language since it closer resembles C which I like since I use HDL to make my life easier.... SystemVerilog seems to be language of the future so I'm not sure if VHDL will have another revision added later down the road in an attempt to get the same simulation features or if 2008 is the end of the line.

Oh realy BadOmen ;-) when i started with fpga's my boss showed me vhdl and verilog and explained me the differences by giving me good practise exercises. after that i made the decision to go for verilog as a few hits on the keyboard were enough to code my thoughts down. and i was used to code in c. by boss had a grin in his face as i heared my decision.

Verilog vs Vhdl | Altera Community

15 Replies

Altera_Forum
Honored Contributor
16 years ago
The customers can also help you decide ;)
Our customers that want to own the HDL code in the projects we develop for them want VHDL, so we code in VHDL. I think I read somewhere that VHDL is more popular in Europe and Verilog is more popular in the US.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
The customers can also help you decide ;)
Our customers that want to own the HDL code in the projects we develop for them want VHDL, so we code in VHDL. I think I read somewhere that VHDL is more popular in Europe and Verilog is more popular in the US.
--- Quote End ---

Yea I came across that article as well. Yea its a good point that the customers can help us decide.

I'm just a bit confused on why my uni makes me learn VHDL instead of Verilog or the basic of both.

Thanks again for all your replies.

Best regards,
Chris
Altera_Forum
Honored Contributor
16 years ago
I think that the important thing when you are learning is to concentrate on one of the two languages. Once you are familiar with the concepts of hardware description languages and learned all the pitfalls, I think it is easy to switch from one language to the other.
I didn't do that much Verilog but I don't think it would be a problem if I needed to learn it one day.
Altera_Forum
Honored Contributor
16 years ago
I fully agree, although I heard quite different opinions at Altera Forum, like below:

--- Quote Start ---
As a VHDL programmer with no Verilog experience these reference designs may as well be written in Swahili and translated into ancient Sumerian! In other words they are completed useless to me.
--- Quote End ---

Seriously, most constructs of both languages have more or less exact equivalents, with a few exceptions. I only occasionally write new Verilog code from the scratch, but I often have to modify or debug existing code. Personally, I miss the option of complex, structured types in Verilog, so I would prefer System Verilog, if I'm required to use Verilog for new designs. I also see an advantage of VHDL in type checking that pays for avoidance of popular coding errors, as mentioned previously in this thread.
Altera_Forum
Honored Contributor
16 years ago
This thread has been really promising.. It definitely cleared my confusion

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Verilog vs Vhdl

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