Verilog vs Vhdl

I fully agree, although I heard quite different opinions at Altera Forum, like below:

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As a VHDL programmer with no Verilog experience these reference designs may as well be written in Swahili and translated into ancient Sumerian! In other words they are completed useless to me.

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Seriously, most constructs of both languages have more or less exact equivalents, with a few exceptions. I only occasionally write new Verilog code from the scratch, but I often have to modify or debug existing code. Personally, I miss the option of complex, structured types in Verilog, so I would prefer System Verilog, if I'm required to use Verilog for new designs. I also see an advantage of VHDL in type checking that pays for avoidance of popular coding errors, as mentioned previously in this thread.