Verilog Testbench

Does Altera Quartus II support Verilog testbench? If yes, how to run a Verilog testbench using QuartusII?

Suppose I have a 2 to 1multiplexer below:

//*********************************************************

module mux_2to1(Y, A, B, sel);

//*********************************************************

output [15:0] Y;

input [15:0] A, B;

input sel;

reg [15:0] Y;

always @(A or B or sel)

if (sel == 1'b0)

Y = A;

else

Y = B;

endmodule

A testbench is created as below:

`timescale 1ns / 100ps

//*********************************************************

module Test_mux_2to1;

//*********************************************************

wire [15:0] MuxOut; //use wire data type for outputs from instantiated module

reg [15:0] A, B; //use reg data type for all inputs

reg sel; // to the instantiated module

reg clk; //to be used for timing of WHEN to change input values

// Instantiate the MUX (named DUT {device under test})

mux_2to1 DUT(MuxOut, A, B, sel);

//This block generates a clock pulse with a 20 ns period

always

# 10 clk = ~clk;

//This initial block will provide values for the inputs

// of the mux so that both inputs/outputs can be displayed

initial begin

$timeformat(-9, 1, " ns", 6);

clk = 1’b0; // time = 0

A = 16'hAAAA; B = 16'h5555; sel = 1'b0;

@(negedge clk) //will wait for next negative edge of the clock (t=20)

A = 16'h0000;

@(negedge clk) //will wait for next negative edge of the clock (t=40)

sel = 1'b1;

@(negedge clk) //will wait for next negative edge of the clock (t=60)

B = 16'hFFFF;

@(negedge clk) //will wait for next negative edge of the clock (t=80)

A = 16'hA5A5;

@(negedge clk) //will wait for next negative edge of the clock (t=100)

sel = 1'b0;

@(negedge clk) //will wait for next negative edge of the clock (t=120)

$finish; // to shut down the simulation

end //initial

// this block is sensitive to changes on ANY of the inputs and will

// then display both the inputs and corresponding output

always @(A or B or sel)

# 1 $display("At t=%t sel=%b A=%h B=%h MuxOut=%h",

$time, sel, A, B, MuxOut);

endmodule

How to test the multiplexer with the testbench using Quartus II?

Thank you