[VERILOG] Rule D101: Data bits are not synchronized when transferred between ...

If the processor bus isn't synchronized to the PLL clock, there's a certain chance that bus signals change simultaneous with the clock edge and cause a timing violation. You likely get inconsistent address or data words and rarely metastable events.

There are several ways to overcome the situation, but they always involve synchronization stages and respective delays. E.g. if you follow the suggestion by a_x_h_75, the bus control signals must be synchronized by double DFFs before they can be used in the synchronous clock domain.