[VERILOG] Rule D101: Data bits are not synchronized when transferred between ...

The RAM block you've generated will be expecting a synchronous address presented to it. This means the address must be generated from the same clock domain you are using to drive the RAM block - i.e. 'pll_clk'.

By latching 'address_register' on a rising edge of 'ale' you are creating a separate domain which is what Quartus doesn't like.

You need to generate 'address_register' in a clocked always block, driven by 'pll_clk'. Within this always block test 'ale' and 'cs_n' for the conditions you need, on every posedge of clock, and latch your 'address_register' accordingly.

Note: the 'data' and 'wren' signals on the RAM will need to be generated from the same clock domain as well.