Verilog reviewing

Hello,

I'd like to know if somebody's heard about Verilog reviewing script. Actually, I made many IPs and I reviewed all of them by myself to delete redundancies. For example, when a signal is set to '1' in a state machine and when this signal is always '1' previous to the assertion, it is a redundancy.

Does somebody know a script or methods to detect this redundancy ?

Best regards,

Julien.