Verilog real functions and compile time

I am trying to generate a compile-time specified LUT based on static inputs.

You are incorrect in that it is not synthesizable in VHDL. The code below will synthesize with no problems and yield warnings stating the output is stuck at VCC or GND - which is understandable since it obviously doesn't change.

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
entity math_real_test is
  port (
    y   :   out signed(31 downto 0)
  ) ;
end entity ; -- math_real_test
architecture arch of math_real_test is
    function f_real( x : in real ) return real is
    begin
        return 5.74857*(x + 0.7071) ;
    end function ;
begin
    
    y <= to_signed( integer(4096.0 * f_real( 1.0 )), y'length ) ;
end architecture ; -- arch

Are there any other questions or suggestions you may have as to being able to do this in Verilog? Should I be looking at SystemVerilog instead of regular Verilog?