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Altera_Forum's avatar
Altera_Forum
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10 years ago

Verilog Question with Quartus.

I use verilog in my Quartus designs and like using the "parameter" statements. When I design a new module and use the statements everything works fine. My problem is when I change the value of the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thank-you for your reply!!

I'm using the "parameter" statement in the verilog source file not through Quartus. I am using an older version of Quartus which is version 9.1. (last time we licensed it) I wonder if this could be a problem in this old version. Also I don't see a "clean" under the project menu. Could this also be a feature in newer versions of Quartus? (Maybe I'm just blind) I'm not familiar with what files can be deleted before compiling (like C object files) that might fix the problem.

Any help would be greatly appreciated!

Brandon