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Hey everybody i have a question that i can't solve.
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You have not tried very hard then :)
I've posted plenty of example designs that include hexadecimal decoders in both VHDL and SystemVerilog. Those designs were not for the DE1-SoC, but that is only a matter of pin assignments.
Here's one in Verilog
http://www.alteraforum.com/forum/showthread.php?t=34391 Here's a DE2 project in VHDL
http://www.alteraforum.com/forum/showthread.php?t=33462 These examples will not "do your homework" for you, but they will help you get started. The members of this forum try not to do student's homework for them, but we do help when you show you have got something started, and get stuck.
Your plan should be modified slightly. You should use the on-board clock for the clock source, not the KEY1 signal. Push buttons "bounce" when you press them, so you would end up with multiple clock edges for each button press. Depending on the hardware design, there might be Schmitt trigger debouncing on the board, or you might need to add it using FPGA logic. Look at the schematics for the board, and use SignalTap II to trace the activity on the KEY1 input while using the on-board clock as a clock source. Since the KEY signal is asynchronous, you will need to use a synchronizer circuit (read about them in the Quartus handbook).
Your design would then use the synchronized version of KEY1 to create a single clock pulse each time KEY1 is pressed. This enable pulse would enable the sum registers.
Make sure you write a testbench for your design. It can seem like a lot of effort to learn both Quartus and Modelsim when you are beginning to learn the languages, however, they're both useful tools.
Cheers,
Dave
Honored Contributor
