Honored ContributorHello all.
Is there any way to force synthesizer to round fractional parameters? For example: parameter N=clock_rate*t_delay, where clock_rate and t_delay are real, should in result give me an integer?
Honored ContributorIf the language doesn't already support it (not sure myself, never needed to use it before directly in HDL) then a simple little function should do the trick. You could keep dividing the parameter by ten and reassembling the digits until the value is less than 1.
Normally when I need such a thing it's in a SOPC Builder/Qsys component and I handle this sort of thing in .tcl and hand off the integer number to the HDL.
