Verilog: multiple conditions inside an if statement

I have a 2D memory i created. 7X16 size, Ii.e 5 rows 16 bit each.

i have 2 8 bit data coming in, and i want to fill 5 rows of the memory with the data.

• first set of data will go automaticly to the memory MEM
• then for each time i get a data i check if it was already saved in memory ( with a parameter buffer):

• if not put it in the next available address

• if yes, do nothing and increase counter x(counter for that row) by one

• if all memory addresses are filled, just deal with counters, any FLUSH new data

the code is a bit messy as i deal with all these at a single clock.

pseudo code:

i just want to emphasis the code works.it simulates and synthesised on FPGA and seems to work ok. i just think its a mess and prone to bugs.

if(index ==0)
MEM<={data1,data2}else if (in_data1<MEM+3 && in_data1>MEM-3 && in_data2<MEM+3 && in_data2>MEM-3)
....increase counter0else if(index ==1)
MEM<={data1,data2}
else if (in_data1<MEM+3 && in_data1>MEM-3 && in_data2<MEM+3 && in_data2>MEM-3)
....increase counter1.... and so on untill
else if (in_data1<MEM+3 && in_data1>MEM-3 && in_data2<MEM+3 && in_data2>MEM-3)
....increase counter4

I feel like its a very messy way. So a few of questiins:

1. Is the arithmetic operation i use inside the "if statement" ok? Is it acceptable?

2. How many logic statement can i put inside the if?

3. because i sweep only 5 memory addresses, i decided to to all these in a single clock. It works but it seems messy to me, any sugestions?