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Altera_Forum's avatar
Altera_Forum
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13 years ago

Verilog 'include in Quartus

Hi, I'm trying to use the following header constructs in verilog to be able to use parameterised modules defined by a header file. Header File cut down example code : (basically just para...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Even though modelsim supports this, you would be much better off writing your code as

module MasterTopLevel # (

`include "Header.v"

)

You would get better syntax error messages if there were problems with your code and you included it this way.