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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Verilog include file not found using 12.1sp1 Qsys (quartus_map) when opening .qsys

Hi, About a month ago, I started porting a design to Quartus 12.1 sp1 to Qsys from Quartus 9.0 SOPC. Everthing ported file and I was able to generate my Qsys file. Then mysteriously on Friday, my ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I solved this by adding the path to the .vh file to the Project Libraries under Settings.

  • SSumm3's avatar
    SSumm3
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thank you.