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Junyong's avatar
Junyong
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Verilog HDL Modeul instantiation error

Hello all, I'm trying to compile "Stratix 10-Tx PAM4 2x51 Gbps with SMA Design Example 18.1" with my Strati10 Tx Signal Integrity Dev Kit. I got an error message below during compilation: Error(1...
Hdl
  • FvM's avatar
    FvM
    2 years ago
    Hi,
    guess you are using a newer version than Quartus 18.1? The example design built with 18.1 will probably need IP regeneration or even some modifications to work with newer Quartus versions. Problems of this kind have been frequently reported.
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
Hi,
guess you are using a newer version than Quartus 18.1? The example design built with 18.1 will probably need IP regeneration or even some modifications to work with newer Quartus versions. Problems of this kind have been frequently reported.
Junyong's avatar
Junyong
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Thank you for your reply, FvM.

The version of Intel Quartus Prime Pro installed on my PC is 18.0.

It would be due to the version as you said. I'll try with Quartus 18.1.

Best Regards,

Junyong