Verilog HDL CODE Help!

The UD counter looks ok.

The MUX uses a command I don't know.

--- Quote Start ---

assign mux_out = (sel)?SOURCE0_IH:SOURCE1_IH:SOURCE2_IH:SOURCE3_IH: SOURCE4_IH:SOURCE5_IH:SOURCE6_IH:SOURCE7_IH;

--- Quote End ---

I only use the conditional operator (?) as a ternary operator. Don't know if can be used in this sense.

I would use a case statement:

--- Quote Start ---

reg mux_out;

always @(sel,SOURCE0_IH,SOURCE1_IH, etc.)

case (sel)

3'b000: mux_out = SOURCE0_IH;

3'b001: mux_out = SOURCE1_IH;

...

default: mux_out = 1'b0;

endcase

--- Quote End ---