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Altera_Forum
Honored Contributor
Honored ContributorVerilog Error
Could you please let me know how to declare a synthesizable array of constants? The constants are shown in the define directive. The below is giving an error. I am new to verilog . Thanks `de...
Altera_ForumHonored Contributor
Honored Contributorthe folder you missed.
the message tells you "C:/modeltech_pe_10.1b/uvm-1.1a/../verilog_src/uvm-1.1a/src/AIC_package.v " which means "C:/modeltech_pe_10.1b/verilog_src/uvm-1.1a/src/AIC_package.v " I don't know why modelsim requires that path. but the message tells you, you need it anyway. just try it and research the reason in someday later.
