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Altera_Forum's avatar
Altera_Forum
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10 years ago

Verilog Error

Could you please let me know how to declare a synthesizable array of constants? The constants are shown in the define directive. The below is giving an error. I am new to verilog . Thanks `de...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

you should try to create the folder and put the file "AIC_package.v "

I think then the simulation works.

just for now , that is enough for you isn't it?

try it anyway.