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Altera_Forum
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10 years ago

Verilog Error

Could you please let me know how to declare a synthesizable array of constants? The constants are shown in the define directive. The below is giving an error. I am new to verilog . Thanks `de...
Altera_Forum's avatar
Altera_Forum
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10 years ago

source files are in C:/work/aaa/bbb/ccc/ddd/xly and testbench in C:/work/aaa/bbb/ccc/ddd/xly/sim.

C:/work/aaa/bbb/ccc/ddd/xly/AIC_package.v

C:/work/aaa/bbb/ccc/ddd/xly/AICController.v

C:/work/aaa/bbb/ccc/ddd/xly/sim/AIC_tb.v

The script is run from C:/work/aaa/bbb/ccc/ddd/xly/sim

The script contains the following

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/AIC_package.v"

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/AICController.v"

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/sim/AIC_tb.v"

vsim work.AIC_tb.

I am confused about this path. This does not exist. Actually the file AIC_package.v is never placed in the folder where ModelSim is reporting error. Its placed alongside its main file AICController.v in C:/work/aaa/bbb/ccc/ddd/xly.