Verilog Error

Thanks, it helped me a lot.

I have prepared a script file and am now compiling the files. The commands in the script are as shown below

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/AIC_package.v"

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/AICController.v"

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/sim/AIC_tb.v"

# Modifying modelsim.ini

# Model Technology ModelSim PE vlog 10.1b Compiler 2012.04 Apr 27 2012

# Model Technology ModelSim PE vlog 10.1b Compiler 2012.04 Apr 27 2012

# ** Error: C:/work/aaa/bbb/ccc/ddd/xly/AICController.v(18): Cannot open `include file "C:/modeltech_pe_10.1b/uvm-1.1a/../verilog_src/uvm-1.1a/src/AIC_package.v".

# -- Compiling module AICController

I could not figure out why its not getting the include file AIC_Package.v