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Altera_Forum's avatar
Altera_Forum
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10 years ago

Verilog Error

Could you please let me know how to declare a synthesizable array of constants? The constants are shown in the define directive. The below is giving an error. I am new to verilog . Thanks `de...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The trouble is not your defines. With Verilog, you cannot initialise a 2D array in that way.

You should instead use an initial block: 


initial begin
    IDATA = DATA_0;
    IDATA = DATA_1;
    ...
end

Also, you appear to have only 8 initialisation values, but there are 32 elements in the array to be initialised.