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Altera_Forum
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15 years ago

verilog 'default' value in quartus throws Err10818

Hi all, yesterday I got a problem while adapting an foreign project in verilog for my testboard. The code includes a lot of lines where a kind of default value has been defined and quartus alwa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You should stick to the standard process model to be sure it can be synthesized: 

  process (clock,reset)
  begin
    if (reset='1') then
      -- reset condtions
    elsif rising_edge(clock) then
      -- clocked actions
    end if;
  end process;

Don't try to do anything on the falling edge of the clock in the same process.