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Altera_Forum
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15 years ago

verilog 'default' value in quartus throws Err10818

Hi all, yesterday I got a problem while adapting an foreign project in verilog for my testboard. The code includes a lot of lines where a kind of default value has been defined and quartus alwa...
Altera_Forum's avatar
Altera_Forum
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15 years ago

ok,

http

www<dot>altera<dot>com/support/examples/vhdl/v_bidir.html

does not work - also an Error 10818.

The examples seem to be for a PLD.

Is it a FPGA-specific problem???