verilog 'default' value in quartus throws Err10818

Hello again,

quartus is going to drive me crazy.

at first nplttr, no - it didn't work.

So I tried to write the controller for my own memory bus first and earned the same:

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Error (10818): Can't infer register for "fb_data[0]" at SD_controller_FlexBus.vhd(26) because it does not hold its value outside the clock edge

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for

LIBRARY ieee;
USE ieee.std_logic_1164.all;
    
ENTITY SD_CONTROLLER_FB IS
    GENERIC( BUSWIDTH: natural := 8);
    PORT
    (
        fb_data                                : inout std_logic_vector(7 downto 0);
        fb_addr                                : in std_logic_vector(19 downto 0);
        fb_cs                                    : in std_logic_vector(1 downto 0);
        fb_oe                                    : in std_logic;
        fb_rw                                    : in std_logic;
        fb_ale                                : in std_logic;
        
        clk                                    : in std_logic;
    
        fb_rx_bd                                : out std_logic_vector(BUSWIDTH-1 downto 0);
        fb_tx_bd                                : in std_logic_vector(BUSWIDTH-1 downto 0)
   );
END SD_CONTROLLER_FB;
ARCHITECTURE SD_CONTROLLER_FB_architecture OF SD_CONTROLLER_FB IS
BEGIN
        PROCESS (fb_ale)
        BEGIN
                IF (rising_edge(fb_ale)) THEN
                    fb_data <= "ZZZZZZZZ";
                ELSE
                    fb_data <= "11111111";
                END IF;
        END PROCESS;
END SD_CONTROLLER_FB_architecture;

WHY ? there are 2 damn constants for now ?!

At this stage its so easy that I would be able to solder this circuit.

cheers, eag1e