verilog 'default' value in quartus throws Err10818

Thanks nplttr for your suggestion,

probably this will be the best way.

The whole structure is difficult to understand because I think it's written far to complicated.

It just seemed that I found the real reason for the quartus-error and I have to say, I have hidden the most important part:

always @(posedge wb_rst_i)
aout <= 0;
if (wb_rst_i) begin
   if (...) begin
      if (...) begin
         aout <= 1;
      end
      else begin
         ...
      end
      ...
   end
   ...
end
elseif (...) begin
...
   aout <= 1;
...
end

So I think the main problem quartus has, is that there are both clock edges used due to the 'elseif' in the end.

But why the hell, is it synthesisable when I comment out the first 'aout <= 0' ?