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Altera_Forum
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15 years ago

verilog 'default' value in quartus throws Err10818

Hi all, yesterday I got a problem while adapting an foreign project in verilog for my testboard. The code includes a lot of lines where a kind of default value has been defined and quartus alwa...
Altera_Forum's avatar
Altera_Forum
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15 years ago

This code is badly written.

If you don't have time to rewrite it completely i can give a suggestion.

What if you create two procedural blocks?

One should generate the "aout" signal in a combinatorial way and hence is not synchronized by the clock.

The second one is a simple flip flop that synchronizes the signal.

Maybe that in this way the synthesizer has a simplified life.