Verilog Attribute for Suppressing Any Specific Warnings

Hi,

I have some logic in my big big RTL file were some signals are forcefully assigned to always '0' or '1' as below:-

always @(*) begin

testbus1.error1 <= 1'b0; // here testbus1 is 660-bit wide structure base bus signal & error1 is one of the single bit strcut. in that bus

testbus1.databus <= databusin;

end

At Synthesis phase I am getting a warning which says "Output bit "error1" is fixed to GND".

This warning is OK for me & I want to suppress this using some attribute over this statement. Can I do it? Is there any attribute?

I have lot of such different warnings which I want to suppress, is there any generic attribute for this?

Please see that I don't want to do it with S/W GUI by right clicking on warning & clicking on Suppress message.

Also I already use "(* altera_attribute ="-name MESSAGE_DISABLE <Mess.# >"*)" & /* synthesis altera_attribute="disable_da_rule=\"r101,c104\"" */

but doesn't help for me.

Any idea would be helpful.

Thanks