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frank2597
New Contributor
New ContributorVerilog: Attempting to make a signal high for 5 clock cycles and then remain low
Hello, I am trying to make the signal called ld_tx_data_scope a value of 1 after the first 5 positive edges and remain high for 5 positive edges and then have it go low and stay low. However, simula...
Hi,
Because you haven't initialize the reg ld_tx_toggle. If you had initialized like this reg ld_tx_toggle = 1'b0; You'll get correct simulation like pic below:
Thanks,
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.
ShengN_altera
Super Contributor
Super ContributorHi,
Because you haven't initialize the reg ld_tx_toggle. If you had initialized like this reg ld_tx_toggle = 1'b0; You'll get correct simulation like pic below:
Thanks,
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.
