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Altera_Forum
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14 years ago

Verilog - how to write parameterized RAM that infers a RAM block?

Does anyone know a way to write a RAM in Verilog with parameterized width and byte enables that causes Quartus to infer a RAM block? Since Altera seems to be strongly discouraging direct use of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Use something like this instead.

Beware: I'm not sure I got the indexes order correct. 

    generate
        for(bytelane=0; bytelane < bena_width; bytelane++) begin : lpbl		
				always_ff @ (posedge clk) begin
					if (wena && bena) 
						ram <= wdata;
					q <= ram;
				
				end
				
        end
    endgenerate