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Altera_Forum
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14 years ago

Verilog - how to write parameterized RAM that infers a RAM block?

Does anyone know a way to write a RAM in Verilog with parameterized width and byte enables that causes Quartus to infer a RAM block? Since Altera seems to be strongly discouraging direct use of...
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Altera_Forum
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14 years ago

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No I'm pretty sure in VHDL i could make a generic memory block with byte enables. Something like this:

I haven't tested it, but it should be recognized properly by the synthesizer.

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Interesting. I don't know VHDL, but that looks like it would do what i need. Because of differences in language structure, the analogous construct in SystemVerilog causes the synthesizer to generate a RAM block per byte lane.