Verilog - how to write parameterized RAM that infers a RAM block?

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Judging from the templates, I think VHDL has the same issue. The Altera VHDL templates for RAM with byte enables also requires the body to be changed if the data width is changed.

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No I'm pretty sure in VHDL i could make a generic memory block with byte enables. Something like this:

process(clk)
  begin
    if(rising_edge(clk)) then 
      if(we = '1') then
        for block_num in 0 to bena_width-1 loop
          if(be(block_num) = '1') then
            ram(waddr)(block_num) <= wdata((block_num*8)+7 downto (block_num*8));
          end if;
        end loop;
      end if;
    q_local <= ram(raddr);
  end if;
end process;

I haven't tested it, but it should be recognized properly by the synthesizer.