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However, what the synthesizer actually complains about is the appearance of ram[addr] in a combinatorial expression, since the ram block does not support an unregistered read. It does not recognize that the entire expression is just describing the behavior of the RAM, and actually tries to map this as an external path.
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It's possibly asking too much that the synthesis tool should be able to accept arbitrary equivalent bevavioral descriptions for inference. In the present case, I'm also not sure if it's strictly equivalent.
But I understand that your point is implementing byte enables in a behavioral description.
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Unfortunately this uses a minimum of bena_width RAM blocks regardless of the total size of the RAM because Quartus will not combine them.
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Can you please give an example in which regard the
recommended hdl style uses more RAM than required according to the hardware properties?
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