Verilog - how to write parameterized RAM that infers a RAM block?

--- Quote Start ---

I wrote an answer on another post talking about the recommended hdl styles (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) to infer proper memory blocks and saw they have an example of a memory with byte enables, on page 11-31. Maybe this will work?

--- Quote End ---

It "works", but the parameterization is broken in that the module body must be changed to support a different data width. It is the same as the SystemVerilog template that is accessible through the Quartus text editor.