Verilog - how to write parameterized RAM that infers a RAM block?

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Could you infer several memory blocks connected in parallel, each one of them handling a 8-bit data bus? Then you use the byte enables to generate write commands only to the relevant blocks.

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Yes, this works fine and is easily implemented by putting the always_ff block inside the generate for loop. Unfortunately this uses a minimum of bena_width RAM blocks regardless of the total size of the RAM because Quartus will not combine them.