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Altera_Forum
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14 years ago

Verilog - how to write parameterized RAM that infers a RAM block?

Does anyone know a way to write a RAM in Verilog with parameterized width and byte enables that causes Quartus to infer a RAM block? Since Altera seems to be strongly discouraging direct use of...
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Altera_Forum
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14 years ago

Could you infer several memory blocks connected in parallel, each one of them handling a 8-bit data bus? Then you use the byte enables to generate write commands only to the relevant blocks.