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Altera_Forum
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14 years ago

Verilog - how to write parameterized RAM that infers a RAM block?

Does anyone know a way to write a RAM in Verilog with parameterized width and byte enables that causes Quartus to infer a RAM block? Since Altera seems to be strongly discouraging direct use of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Open a verilog file in Quartus II and go to Edit -> Insert Template -> Verilog. There are a number of Verilog RAM inference files there.

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The first of my two test instantiations, the one that works but is not properly parameterized, is based directly on those templates. I was hoping to find a way to fix the parameterization.