Verify .sof file

Good afternoon,

We have developed FPGA code that we are programming to a Cyclone II FPGA. To do this we are using Quartus II v13.0SP1. We have successfully programmed and tested the code. We now have to hand off the code to another department and they are looking for a verification process to ensure the code has been successfully added to the FPGA. Reading into this it seems we could use the checksum. Now as we are loading via JTAG using the .sof file that was created after compiling. The only option I can check though is "Program/Configure". How come I can not use any of the other programming otpions; mainly "Verify".

I of course can see the checksum of my file before clicking program, but want to verify that is what the FPGA received after it has been programmed.