vectors in VHDL

quite easy:

signal my_sig : std_logic_vector(N-1 downto 0);

no i mean i want to have N vectors that their length are different

i wanna write a loop for it LIKE:

for i in 0 to N loop

.....<= std_logic_vector(i downto 0);

end loop;

its ok!but what i should write instead of the blank?

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can you repost the code with a real example. Std_logic_vector is a type and you cannot index into it. You are also implying you want to assign an ever decreasing sized vector - you're not allowed to have an array of vectors with different sizes.

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thanks alot my friend

i wanna translate haar algorithm to vhdl code

plz see these pictures:

http://i41.tinypic.com/35ksllh.jpg

&

http://i39.tinypic.com/2u6ftyx.png

how i can do this? i though for writing this code i need to have a loop that makes different vectors.