VCS error Error-[URMI] Unresolved modules in cyclonev_atoms_ncrypt.v

I gave it a try. I created a project using the qip file from the qsys block.

The project was successfully analyzed and elaborated in Quartus. The 3-rd party simulation scripts were generated.

I executed the generated tcl file:

quartus_sh -t balmas_exmple_vcsmx_rtl_verilog.tcl

I got the message that the compilation was successful. I didn't get anything about the elaboration.

Then I tried to elaborate the design using the command:

vcs -debug_access+all nios_sys -kdb -lca

I'm getting a different type of errors. During the design elaboration I see multiple errors:

Error-[UPIMI-E] Undefined port in module instantiation
/<project path>/quartus_prj_nios_sys_only/nios_sys112_verilog/synthesis/submodules/alt_mem_ddrx_controller.v, 1072
Port "local_zqcal_req" is not defined in module 'alt_mem_ddrx_input_if'
defined in
"/<installation path>/quartus_15.0/quartus/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v",
25
Module instance: alt_mem_ddrx_input_if
#(.CFG_LOCAL_DATA_WIDTH(CFG_LOCAL_DATA_WIDTH),
.CFG_LOCAL_ID_WIDTH(CFG_LOCAL_ID_WIDTH),
.CFG_LOCAL_ADDR_WIDTH(CFG_LOCAL_ADDR_WIDTH), .CF ...

I can downgrade severity of these errors (-error=noUPIMI-E) , but I cannot downgrade/suppress the errors:

Error-[TMIPC] Many port connections
/<project path>/quartus_prj_nios_sys_only/nios_sys112_verilog/synthesis/submodules/alt_mem_ddrx_controller.v, 1321
Too many module or UDP instance port connections:
Too many port connections are found for instance "tbp_inst" of module
"alt_mem_ddrx_tbp"
Source info: alt_mem_ddrx_tbp #(.CFG_CTL_TBP_NUM(CFG_CTL_TBP_NUM),
.CFG_CTL_SHADOW_TBP_NUM(CFG_CTL_SHADOW_TBP_NUM),
.CFG_ENABLE_SHADOW_TBP(CFG_ENABLE_SHADOW_TBP), .CFG_DWI ...
Module "alt_mem_ddrx_tbp" is defined at
"/<installation path>/quartus_15.0/quartus/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v",
25

I see 4 errors and all of them are from the same encrypted file:

/<installation path>/quartus_15.0/quartus/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v