(vcom-1600) No feasible entries for subprogram

This api_if signal has declaration of mm_mstr_vhdl_if_t which is below type:

type mm_mstr_vhdl_if_base_t is record

req : std_logic_vector (MM_MSTR_INIT downto 0);

ack : std_logic_vector (MM_MSTR_INIT downto 0);

data_in0 : integer;

data_in1 : integer;

data_in2 : std_logic_vector (MM_MAX_BIT_W - 1 downto 0);

data_out0 : integer;

data_out1 : integer;

data_out2 : std_logic_vector (MM_MAX_BIT_W - 1 downto 0);

events : std_logic_vector (MM_MSTR_EVENT_MIN_COMMAND_QUEUE_SIZE downto 0);

end record;

type mm_mstr_vhdl_if_t is array(MAX_VHDL_BFM - 1 downto 0) of mm_mstr_vhdl_if_base_t;

Can you suggest how to declare that in my test program? Thanks