Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

(vcom-1600) No feasible entries for subprogram

Dear Good people, I was using following code while simulating it through modelsim, it shows following error : (vcom-1600) No feasible entries for subprogram "avalon_write". Can you guys please give ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The api_if parameter in your avalon_write call is not the same types than the one in the procedure declaration. In the procedure declaration: 

procedure avalon_write(
addr : in std_logic_vector (AV_ADDRESS_W-1 downto 0);
data : in std_logic_vector (AV_DATA_W -1 downto 0);
signal api_if : inout mm_mstr_vhdl_if_t
)

the api_if signal is of type mm_mstr_vhdl_if_t, but in your test bench you declared the api_if signal as a std_logic_vector: 

signal api_if : std_logic_vector (MAX_VHDL_BFM - 1 downto 0);