vcd file generation with vhdl testbench

I am working on power analysis of general DSP application in Quartus-II 9.1. As signal activity file (saf) or value change dump (vcd) files are required for the power analysis in Quartus-II; that can be generated by vector waveform file level simulation in Quartus-II.

Because I am working on an application where input samples are in multiple of 1000s and can be changed frequently. So the vector waveform file simulation does not suit my application that’s why I am bothering to simulate the design in ModelSim with text I/O files as input and generate vcd file.

In this regards, initially I simulated the top level design with few sample of inputs using ‘do’ file script and force statements, ‘vcd’ file was generated properly.

But when I executed the testbench of same design reading input from ‘input.txt’ and place output in ‘text.out’; there was no information in vcd file.

1. I wonder for the procedure to execute vhdl testbench with text I/O inputs (not force statement) and generate vcd file in ModelSim; while main instance(s) compiled in Quartus-II.

2. Or even simply generate the vcd file in ModelSim with vhdl testbench reading I/O files?

Thanks in advance for your help and cooperation in this regards.

Kind Regards