Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi, I have the same problem where I have the following contents in the generated vcd file:
$date Tue Dec 28 22:20:00 2010 $end $version ModelSim Version 6.6c $end $timescale 1ps $end I am using Verilog, and hence I do not have any 'Design instance name' as opposed to that of VHDL. Correct me if I'm wrong. Any idea here?