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Altera_Forum's avatar
Altera_Forum
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17 years ago

Variables are showing abnormal contents in Time simulation

I am new to VHDL and using Quartus II to synthesis my program. My functional simulation is ok but when I am doing time simulation the values of variables : queue_length and x10_queue are showing some...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Also make sure you are using the right math packages (unsigned vs. signed). Sounds like the previous poster's comment was most likely though. Make sure your clock is going at the period that you mean it to be going at.

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Thanks.

The problem was not for incorrect usage of the variable.Its for clock higher frequency , incorrect hold time and setup time of some signals.

One should care about the usage of variables in VHDL.

Thanks for remind me about this.