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Altera_Forum's avatar
Altera_Forum
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17 years ago

Variables are showing abnormal contents in Time simulation

I am new to VHDL and using Quartus II to synthesis my program. My functional simulation is ok but when I am doing time simulation the values of variables : queue_length and x10_queue are showing some...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Quartus creates a vwf file with a default grid of 10 ns. I'm almost sure your Clock period is 10 ns. and your design is slower.

Look for the classing timing analizer or time quest and look for your max. operating frequency.

Try with a higher clock period

--- Quote End ---

Thanks a lot.

Yas.You are right, The problem was for higher clock frequency.

There was also some problem for some signals setup time and hold time.

Problem solved ! ! !