Utilization report - how to find out how many LUTs are used?

I'm trying to systematically analyse some results I've obtained with Altera OpenCL, having done so for an equivalent design under Vivado HLS.

For the latter I am using LUTs and FFs utilization for discussion of the Pareto Optimization process. However, on the Altera side multiple *stuff* is reported.

Say the report acl_quartus_report.txt

ALUTs: 136630
Registers: 232,832
Logic utilization: 121,749 / 172,600 ( 70 % )
I/O pins: 305 / 664
DSP blocks: 7 / 1,590
Memory bits: 3,811,290 / 41,246,720
M20K blocks: 1,224 / 2,014
Actual clock freq: 222.60999963
Kernel fmax: 222.61
1x clock fmax: 222.61
2x clock fmax: 10000
Highest non-global fanout: 5038

I know how many registers there are, based on the Stratix V specification datasheets, so I can report utilization levels of registers as a percentage. However, an ALUT, AFAIK, is something less obvious. For the one it is not reported how many ALUTs a device has. Correct me if I'm wrong. As I understand, a single LUT can provide 2 ALUTs, so 2 ALUTs can be using a single LUT, or each ALUT can be using an LUT, right? On the other hand, I also don't know how many LUTs the FPGA has.

I know ALMs, and that ALMs in Stratix V have 2 LUTs and 4 FFs. But the logic utilization given by A-B+C yields a measure of how many ALMs are utilized based on LUT+FF utilization, those that use only LUT and FF but can be densely packed, and then those that cannot be packed (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05172012_146.html).

For the same project, the area.rpt file contains

Total: LEs = 163549  FFs = 328203  RAMs = 1704  DSPs = 70
Global_resources: LEs = 28908  FFs = 48290  RAMs = 104  DSPs = 0
Const_resources: LEs = 0  FFs = 0  RAMs = 0  DSPs = 0
LSU_resources: LEs = 49441  FFs = 152985  RAMs = 987  DSPs = 0
FP_resources: LEs = 0  FFs = 0  RAMs = 0  DSPs = 0
Local_mem_resources: LEs = 0  FFs = 0  RAMs = 0  DSPs = 0
Reg_State_resources: LEs = 9471  FFs = 22876  RAMs = 84  DSPs = 0
RAM_State_resources: LEs = 4599  FFs = 3717  RAMs = 147  DSPs = 0
MrgBr_State_resources: LEs = 0  FFs = 1568  RAMs = 0  DSPs = 0
Other_State_resources: LEs = 490  FFs = 490  RAMs = 0  DSPs = 0
Other_resources: LEs = 32032  FFs = 47257  RAMs = 98  DSPs = 70
------------
LEs: 47.378 %
FFs: 47.5381 %
RAMs: 84.6077 %
DSPs: 4.40252 %
Util: 92.7939 %

Based on that I get a total number of LEs in my device of (260,686/43.3508%) = 601,340 LEs. So there are 601340 LEs. Does this mean my design is using 1 LUT, 2 LUTs? What about that 1.25LE = 1ALUT metric, reportedly, http://electronics.stackexchange.com/questions/81312/what-are-alms-les-and-aluts. But if I apply the same math to FFs I get (559,606/44.2226%) = 1,265,429. But I only have 690,000 Registers on the Stratix V. Are registers not FFs?

How do I find out the number of ALUTs the FPGA has?

Bottomline is, I want LUTs and FFs. Can I have it?

Either I can convert LEs to LUTs, or I can convert ALUTs to LUTs, no?

In the end, I'm not likely to be comparing LUTs utilization of Altera vs. Xilinx. But if the metrics used are different, people then to focus on how the two cannot be compared, even if in the end you don't ever so slightly compare them. What am I missing here?

Thanks for you kind help.