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Altera_Forum
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13 years ago

using the LPM_ADD_SUB mega function

Hi, I developed a 4-bit SIGNED adder with a carry bit using the lpm_add_sub megafunction in VHDL in Quartus II 11.1. I'm using a DE1 board with a Cyclone II to verify the component. Here's the pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Try (+1 + -1) with 5 bits. You'll notice that a carry from fourth to fifth bit takes place.

In signed add, the carry bit does not indicate an overflow.