Using tasks with wait segments in Verilog

The use of 'automatic' means the verilog compiler/simulator must make the task re-entrant, so it must copy all input/outputs to temp variables during execution. So this probably means you are calling the task multiple times in parallel, while older invocations are still executing, because of your builtin time delays.

As an example, in old style verilog, I have the task just reference the module signals in its called context, and not pass everything as arguments. I also don't call the task again until I know the existing call has finished (which in my case calling it multiple times in parallel does not make any sense).

Example:

    reg          sd_dat_adr = 0;
    reg         sd_dat_wen = 0;
    reg          sd_dat_din = 0;
    wire          sd_dat_dout;
    task rd_buf;
    input  fradr;
    input  toadr;
    integer     i;
    begin
    @(posedge clk)# TPD ;
    $write("\n");
    for (i = fradr; i <= toadr; i = i+1)
    begin
    sd_dat_adr = i;
    sd_dat_wen = 0;
    sd_dat_din = 0;
    @(posedge clk)# TPD ;
    @(posedge clk)# TPD ;
    @(posedge clk)# TPD ;
    if (sd_dat_adr % 16 == 0) $write("%h:", sd_dat_adr);
    $write(" %h", sd_dat_dout);
    if (sd_dat_adr % 16 == 15) $write("\n");
    end
    @(posedge clk)# TPD ;
    $write("\n");
    end
    endtask // rd_buf

And then in my testbench I just call the task when needed:

    initial
    begin
    init_card(10);
        rd_buf(0,511);
    delay(250);
    $finish;
    end