Using tasks with wait segments in Verilog

Thank you, it works now.

task automatic send_8bit;
	input reg  Y8bit;
	input reg  C8bit;
	ref reg  rx_in;
	integer counter;
	reg PIXEL_IN_Y1;
	reg PIXEL_IN_Y2;
	reg PIXEL_IN_C1;
	reg PIXEL_IN_C2;
	begin
		// Data protocol for the Tamron camera:
		// Y1: Y6 Y5 Y4 Y3 Y2 Y1 Y0
		// Y2: 0  0  0  X  X  X  Y7
		// C1: C6 C5 C4 C3 C2 C1 C0
		// C2: 0  0  0  0  0  C6 C7
		PIXEL_IN_Y1=Y8bit;
		PIXEL_IN_Y2=Y8bit;
		PIXEL_IN_C1=C8bit;
		PIXEL_IN_C2=C8bit;
		PIXEL_IN_C2=C8bit;
		PIXEL_IN_Y2=6'b000XXX;
		PIXEL_IN_C2=5'b00000;
		Y8bit_debug=Y8bit;
		C8bit_debug=C8bit;
		for(counter = 6; counter >=0; counter = counter - 1) 
		begin
		# 1924	//length of 1 data period in ps
			rx_in= PIXEL_IN_Y1;				
			rx_in= PIXEL_IN_Y2;
			rx_in= PIXEL_IN_C1;
			rx_in= PIXEL_IN_C2;
		end
	end
endtask