Using tasks with wait segments in Verilog

In Verilog, input arguments get copied upon entry, and output arguments get copied upon exit of a task or function. If you use Systemverilog, you can change the last argument to a ref, which means rx_in will be a reference to the actual argument instead of a value that gets copied to it.

task automatic send_8bit(
    input reg  Y8bit,
    input reg  C8bit, 
    ref reg  rx_in
);

Most tools now support SystemVerilog just by changing the file extension from *.v to *.SystemVerilog . Note that the task needs to have an automatic lifetime to use the ref argument.

If you are not able to do this, your only other option is for the task to directly modify OUPUT instead of passing it in as an argument to the task.