Using sensitivity list for always block

Yes,the above is fine.

The tools do not propagate clocks through registers, so you'll need to constrain each and every of those signals as a clock in order to get valid timing analysis.

Also, in FPGAs the path from a logic cell to the flip-flops' clock port is very long -- it's a pre-built clock distribution tree. Any "clock" generated clock tends to have large skews in relation to other clocks and makes timing closure harder.